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MBM29LV320TE80/90/10/ MBM29LV320BE80/90/10
Data Sheet (Retired Product)
90/10
MBM29LV320TE80/90/10/MBM29LV320BE80/ Cover Sheet
This product has been retired and is not recommended for new designs. Availability of this document is retained for reference and historical purposes only.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number MBM29LV320TE/BE
Revision DS05-20894-5E
Issue Date July 31, 2007
Data
Sheet
(Retired
Product)
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MBM29LV320TE/BE_DS05-20894-5E July 31, 2007
SPANSION
Data Sheet
TM
Flash Memory
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION TM product. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions.
TM
memory
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20894-5E
FLASH MEMORY
CMOS
32 M (4 M x 8/2 M x 16) BIT
MBM29LV320TE 80/90/10 MBM29LV320BE80/90/10
DESCRIPTION
The MBM29LV320TE/BE is 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words of 16 bits each. The device is offered in a 48-pin TSOP (1) and 63-ball FBGA packages. This device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard device offers access times 80 ns, 90 ns and 100 ns, allowing operation of high-speed microprocessors without wait state. To eliminate bus contention the device has separate chip enable(CE), write enable(WE) and output enable (OE) controls. (Continued) MBM29LV320TE/BE 80 VCC = 3.3 V +0.3 V -0.3 V 80 80 30 90 90 35 90 100 VCC = 3.0 V +0.6 V -0.3 V 100 100 35
PRODUCT LINE UP
Part No. Power Supply Voltage (V)
Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns)
PACKAGES
48-pin plastic TSOP (1) Marking Side 48-pin plastic TSOP (1) 63-ball plastic FBGA
Marking Side (FPT-48P-M19) (FPT-48P-M20) (BGA-63P-M01)
(Continued)
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The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This invokes the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This invokes the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically time the erase pulse widths and verify proper cell margin. A sector is Typically erased and verified in 1.0 second. (If already completely preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle is completed, the device internally resets to the read mode. The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the reset. Resetting the device enables the system's microprocessor to read the boot-up firmware from the Flash memory. Fujitsu Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
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MBM29LV320TE/BE80/90/10
FEATURES
* 0.23 m Process Technology * Single 3.0 V Read, Program, and Erase Minimized system level power requirements * Compatible with JEDEC-standard Commands Use the same software commands as E2PROMs * Compatible with JEDEC-standard Worldwide Pinouts 48-pin TSOP (1) (Package suffix : TN - Normal Bend Type, TR - Reversed Bend Type) 63-ball FBGA (Package suffix : PBT) * Minimum 100,000 Program/Erase Cycles * High Performance 80 ns maximum access time * Sector Erase Architecture Eight 4 K word and sixty-three 32 K word sectors in word mode Eight 8 K byte and sixty-three 64 K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture T = Top sector B = Bottom sector * HiddenROM Region 256 byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC Input Pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status At VACC, increases program performance * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * Sector group protection Hardware method disables any combination of sector groups from program or erase operations * Sector Group Protection Set function by Extended sector group protection command * Fast Programming Function by Extended Command * Temporary sector group unprotection Temporary sector group unprotection via the RESET pin. * In accordance with CFI (Common Flash Memory Interface) *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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PIN ASSIGNMENTS
TSOP (1)
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0
MBM29LV320TE/BE Normal Bend
(FPT-48P-M19)
A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY WP/ACC N.C. RESET WE A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
MBM29LV320TE/BE Reverse Bend
A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16
(FPT-48P-M20)
(Continued)
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MBM29LV320TE/BE80/90/10
(Continued) FBGA (TOP VIEW) Marking Side
A8 N.C. A7 N.C. B8 N.C. B7 N.C. C7 A13 C6 A9 C5 D7 A12 D6 A8 D5 E7 A14 E6 A10 E5 F7 A15 F6 A11 F5 A19 F4 A20 F3 A5 F2 A1 G7 A16 G6 H7 J7 K7 L8 N.C. L7 N.C. M8 N.C. M7 N.C.
BYTE DQ15/ VSS A-1 H6 J6 K6
DQ7 DQ14 DQ13 DQ6 G5 H5 J5 VCC J4 K5 DQ4 K4
WE RESET N.C. C4 D4 E4 A18 E3 A6 E2 A2
DQ5 DQ12 G4 H4
RY/BY WP/ ACC C3 A7 A2 N.C. A1 N.C. B1 N.C. C2 A3 D3 A17 D2 A4
DQ2 DQ10 DQ11 DQ3 G3 DQ0 G2 A0 H3 DQ8 H2 CE J3 DQ9 J2 OE K3 DQ1 K2 VSS L2 N.C. L1 N.C. M2 N.C. M1 N.C.
(BGA-63P-M01)
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PIN DESCRIPTION
MBM29LV320 TE/BE Pin Configuration Table Pin A20 to A0, A-1 DQ15 to DQ0 CE OE WE RESET RY/BY BYTE WP/ACC N.C. VSS VCC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Hardware Reset Pin/Temporary Sector Group Unprotection Ready/Busy Output Selects 8-bit or 16-bit mode Hardware Write Protection/Program Acceleration No Internal Connection Device Ground Device Power Supply Function
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BLOCK DIAGRAM
RY/BY Buffer VCC VSS Erase Voltage Generator Input/Output Buffers DQ15 to DQ0 RY/BY
WE BYTE RESET WP/ACC
State Control
Command Register Program Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE OE
STB
Y-Decoder
Y-Gating
Low VCC Detector
Timer for Program/Erase
Address X-Decoder Latch
Cell Matrix
A20 to A09 A-1
LOGIC SYMBOL
A-1 21 A20 to A0 DQ15 to DQ0 CE OE WE RESET BYTE WP/ACC RY/BY 16 or 8
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DEVICE BUS OPERATION
MBM29LV320TE/BE User Bus Operations Table (BYTE = VIH) Operation Auto-Select Manufacturer Code *1 Auto-Select Device Code * Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Group Protection *2, *4 Verify Sector Group Protection *2, *4 Temporary Sector Group Unprotection *5 Reset (Hardware) /Standby Boot Block Sector Write Protection Legend : L = VIL, H = VIH, X = VIL or VIH,
1
CE OE WE L L L L H L L L L X X X L L L L X H H VID L X X X H X X X H H H H X H L
A0 L H H A0 X X A0 L L X X X
A1 L L H A1 X X A1 H H X X X
A6 L L L A6 X X A6 L L X X X
A9 VID VID VID A9 X X A9 VID VID X X X
DQ15 to DQ0 Code Code Code DOUT High-Z High-Z DIN X Code X High-Z X
RESET H H H H H H H H H VID L X
WP/ ACC X X X X X X X X *6 X *6 X *6 X L
Extended Auto-Select Device Code *1
= Pulse input. See "DC CHARACTERISTICS" for voltage levels.
*1: Manufacturer and device codes are accessed via a command register write sequence. See "MBM29LV320TE/ BE Command Definitions Table". *2: See the section on "7. Sector Group Protection" in FUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V 10% *5: Also used for the extended sector group protection. *6: Conditional exceptions are to be noticed as follows: For MBM29LV320TE (SA22, 23) , WP/ACC = VIH. For MBM29LV320BE (SA0, 1) , WP/ACC = VIH.
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MBM29LV320TE/BE User Bus Operations Table (BYTE = VIL) Operation Auto-Select Manufacturer Code *1 Auto-Select Device Code * Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Group Protection *2, *4 Verify Sector Group Protection *2, *4 Reset (Hardware) /Standby Boot Block Sector Write Protection Legend : L = VIL, H = VIH, X = VIL or VIH,
1
CE L L L L H L L L L X X
OE WE L L L L X H H VID L X X X H X X X H H H H X H L
DQ15 /A-1 L L L A-1 X X A-1 L L X X X
A0 L H H A0 X X A0 L L X X X
A1 L L H A1 X X A1 H H X X X
A6 L L L A6 X X A6 L L X X X
A9 VID VID VID A9 X X A9 VID VID X X X
DQ7 to DQ0 Code Code Code DOUT High-Z High-Z DIN X Code X High-Z X
RESET H H H H H H H H H VID L X
WP/ ACC X X X X X X X X *6 X *6 X *6 X L
Extended Auto-Select Device Code *1
Temporary Sector Group Unprotection *5 X
= Pulse input. See "DC CHARACTERISTICS" for voltage levels.
*1: Manufacturer and device codes may also be accessed via a command register write sequence. See "MBM29LV320TE/BE Command Definitions Table". *2: See the section on "7. Sector Group Protection" in FUNCTIONAL DESCRIPTION. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V 10% *5: It is also used for the extended sector group protection. *6: Conditional exceptions are to be noticed as follows: For MBM29LV320TE (SA22, 23) , WP/ACC = VIH. For MBM29LV320BE (SA0, 1) , WP/ACC = VIH.
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MBM29LV320TE/BE Command Definitions Table Command Sequence Read/ Reset*6 Read/ Reset*6 Autoselect Program Chip Erase Sector Erase
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
First Bus Third Bus Bus Bus Write Write Cycle Write Cycle Write Cycle Cycles Req'd 1 3 3 4 6 6 1 1 3 2 2 XXXh F0h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh XXXh 555h AAAh XXXh XXXh XXXh XXXh XXXh 55h AAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh AAh AAh AAh AAh AAh 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h PA XXXh 55h 55h 55h 55h 55h 55h PD
*5
Second
Fourth Bus Fifth Bus Sixth Bus Read/Write Write Cycle Write Cycle Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh F0h 90h A0h 80h 80h 20h 2AAh 555h 2AAh 555h 55h 55h 555h AAAh SA 10h 30h
RA*7 RD*7 IA*7 PA 555h AAAh 555h AAAh ID*7 PD AAh AAh
Erase Suspend Erase Resume Set to Fast Mode Fast Program*1
Word Byte Word Byte
XXXh B0h 30h AAh A0h 90h
Reset from Word Fast Mode*1 Byte Extended Sector Group Protection*2 Query*3
Word
XXXh F0h SPA 60h
3
Byte Word Byte
60h
SPA
40h SPA*7 SD*7

1 3 4 6 4
98h AAh AAh AAh AAh
2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h
55h 55h 55h 55h
555h AAAh 555h AAAh 555h AAAh 555h AAAh
88h A0h 80h 90h

(HRA)
PD AAh 00h
2AAh 555h
55h
HRA
30h
HiddenROM Word Entry Byte HiddenROM Word Program*4 Byte HiddenROM Word Erase*4 Byte HiddenROM Word Exit*4 Byte
PA 555h AAAh XXXh
(Continued)
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(Continued) *1 : This command is valid during Fast Mode. *2 : This command is valid while RESET = VID. *3 : The valid addresses are A6 to A0. *4 : This command is valid during HiddenROM mode (except during HiddenROM mode). *5 : The data "00h" is also acceptable. *6 : Both of these reset commands are equivalent. *7 : The fourth bus cycle is only for read. Notes: * Address bits A20 to A11 = X = "H" or "L" for all address commands except or Program Address (PA) and Sector Address (SA) . * Bus operations are defined in "MBM29LV320TE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" . * RA = Address of the memory location to be read IA = Autoselect read address that sets both the bank address specified at (A19, A18, A17, A16, A15) and all the other A6, A1, A0, (A-1) . PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. * RD = Data read from location RA during read operation. ID = Device code/manufacture code for the address located by IA. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. * SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. * HRA = Address of the HiddenROM area 29LV320TE (Top Boot Type) Word Mode : 1FFFE0h to 1FFFFFh Byte Mode : 3FFFC0h to 3FFFFFh 29LV320BE (Bottom Boot Type) Word Mode : 000000h to 000040h Byte Mode : 000000h to 000080h * The system should generate the following address patterns : Word Mode : 555h or 2AAh to addresses A10 to A0 Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1 * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. * The command combinations not described in "MBM29LV320TE/BE Command Definition Table" are illegal.
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MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table Type Manufacture's Code MBM29LV320TE Device Code MBM29LV320BE Extend Device Code Byte Word Byte Word Byte Word Byte MBM29LV320TE/BE Word Byte Word SA Sector Group Addresses VIL VIH VIH A20 to A12 SA SA SA A6 VIL VIL VIL A1 VIL VIL VIL A0 VIL VIH VIH A-1 *1 VIL X VIL X VIL X VIL X VIL X Code (HEX) 04h 0004h F6h 22F6h F9h 22F9h 19h 0019h 01h*2 0001h*2
Sector Group Protection
VIL
VIH
VIL
*1 : A-1 is for byte mode. At byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
Extended Autoselect Code Table Type Manufacturer's Code
(B)* Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
04h A-1
0
HZ 0 HZ 0 HZ 0 HZ 0 HZ 0
HZ 0 HZ 1 HZ 1 HZ 0 HZ 0
HZ 0 HZ 0 HZ 0 HZ 0 HZ 0
HZ 0 HZ 0 HZ 0 HZ 0 HZ 0
HZ HZ HZ 0 0 0 0 1 1 0 0 0 HZ HZ HZ HZ HZ HZ HZ HZ HZ 0 0 0
0 0 1 1 1 1 0 0 0 0
0 0 1 1 1 1 0 0 0 0
0 0 1 1 1 1 0 0 0 0
0 0 1 1 1 1 1 1 0 0
0 0 0 0 1 1 1 1 0 0
1 1 1 1 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1
(W) 0004h
F6h MBM29LV (B)* 320TE (W) 22F6h Device Code F9h MBM29LV (B)* 320BE (W) 22F9h
Extend (B)* 19h MBM29LV Device 320TE/BE (W) 0019h Code
A-1 0 A-1 0 A-1 0
Sector Group Protection (B) : Byte mode (W) : Word mode HZ: High-Z
(B)*
01h A-1
0
HZ HZ HZ 0 0 0
(W) 0001h
* : At byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address.
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FLEXIBLE SECTOR-ERASE ARCHITECTURE
Sector Address Table (MBM29LV320TE) Sector Size Sector (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 000000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh 0C0000h to 0CFFFFh 0D0000h to 0DFFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh 1F0000h to 1FFFFFh (x16) Address Range 000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh (Continued) 16
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Sector Size Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 (Kbytes/ Kwords) Sector Address SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4
(x8) Address Range 200000h to 20FFFFh 210000h to 21FFFFh 220000h to 22FFFFh 230000h to 23FFFFh 240000h to 24FFFFh 250000h to 25FFFFh 260000h to 26FFFFh 270000h to 27FFFFh 280000h to 28FFFFh 290000h to 29FFFFh 2A0000h to 2AFFFFh 2B0000h to 2BFFFFh 2C0000h to 2CFFFFh 2D0000h to 2DFFFFh 2E0000h to 2EFFFFh 2F0000h to 2FFFFFh 300000h to 30FFFFh 310000h to 31FFFFh 320000h to 32FFFFh 330000h to 33FFFFh 340000h to 34FFFFh 350000h to 35FFFFh 360000h to 36FFFFh 370000h to 37FFFFh 380000h to 38FFFFh 390000h to 39FFFFh 3A0000h to 3AFFFFh 3B0000h to 3BFFFFh 3C0000h to 3CFFFFh 3D0000h to 3DFFFFh 3E0000h to 3EFFFFh 3F0000h to 3F1FFFh 3F2000h to 3F3FFFh
(x16) Address Range 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1F8FFFh 1F9000h to 1F9FFFh (Continued) 17
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MBM29LV320TE/BE80/90/10
(Continued) Sector Size Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 (Kbytes/ Kwords) Sector Address SA65 SA66 SA67 SA68 SA69 SA70 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 X X X X X X 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address Range 3F4000h to 3F5FFFh 3F6000h to 3F7FFFh 3F8000h to 3F9FFFh 3FA000h to 3FBFFFh 3FC000h to 3FDFFFh 3FE000h to 3FFFFFh (x16) Address Range 1FA000h to 1FAFFFh 1FB000h to 1FBFFFh 1FC000h to 1FCFFFh 1FD000h to 1FDFFFh 1FE000h to 1FEFFFh 1FF000h to 1FFFFFh
Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL). The address range is A20 : A0 if in word mode (BYTE = VIH).
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MBM29LV320TE/BE80/90/10
Sector Address Table (MBM29LV320BE) Sector Size Sector (Kbytes/ A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Kwords) Sector Address SA70 SA69 SA68 SA67 SA66 SA65 SA64 SA63 SA62 SA61 SA60 SA59 SA58 SA57 SA56 SA55 SA54 SA53 SA52 SA51 SA50 SA49 SA48 SA47 SA46 SA45 SA44 SA43 SA42 SA41 SA40 SA39 SA38 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 3F0000h to 3FFFFFh 3E0000h to 3EFFFFh 3D0000h to 3DFFFFh 3C0000h to 3CFFFFh 3B0000h to 3BFFFFh 3A0000h to 3AFFFFh 390000h to 39FFFFh 380000h to 38FFFFh 370000h to 37FFFFh 360000h to 36FFFFh 350000h to 35FFFFh 340000h to 34FFFFh 330000h to 33FFFFh 320000h to 32FFFFh 310000h to 31FFFFh 300000h to 30FFFFh 2F0000h to 2FFFFFh 2E0000h to 2EFFFFh 2D0000h to 2DFFFFh 2C0000h to 2CFFFFh 2B0000h to 2BFFFFh 2A0000h to 2AFFFFh 290000h to 29FFFFh 280000h to 28FFFFh 270000h to 27FFFFh 260000h to 26FFFFh 250000h to 25FFFFh 240000h to 24FFFFh 230000h to 23FFFFh 220000h to 22FFFFh 210000h to 21FFFFh 200000h to 20FFFFh 1F0000h to 1FFFFFh (x16) Address Range 1F8000h to 1FFFFFh 1F0000h to 1F7FFFh 1E8000h to 1EFFFFh 1E0000h to 1E7FFFh 1D8000h to 1DFFFFh 1D0000h to 1D7FFFh 1C8000h to 1CFFFFh 1C0000h to 1C7FFFh 1B8000h to 1BFFFFh 1B0000h to 1B7FFFh 1A8000h to 1AFFFFh 1A0000h to 1A7FFFh 198000h to 19FFFFh 190000h to 197FFFh 188000h to 18FFFFh 180000h to 187FFFh 178000h to 17FFFFh 170000h to 177FFFh 168000h to 16FFFFh 160000h to 167FFFh 158000h to 15FFFFh 150000h to 157FFFh 148000h to 14FFFFh 140000h to 147FFFh 138000h to 13FFFFh 130000h to 137FFFh 128000h to 12FFFFh 120000h to 127FFFh 118000h to 11FFFFh 110000h to 117FFFh 108000h to 10FFFFh 100000h to 107FFFh 0F8000h to 0FFFFFh (Continued)
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MBM29LV320TE/BE80/90/10
Sector Size Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 (Kbytes/ Kwords) Sector Address SA37 SA36 SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4
(x8) Address Range 1E0000h to 1EFFFFh 1D0000h to 1DFFFFh 1C0000h to 1CFFFFh 1B0000h to 1BFFFFh 1A0000h to 1AFFFFh 190000h to 19FFFFh 180000h to 18FFFFh 170000h to 17FFFFh 160000h to 16FFFFh 150000h to 15FFFFh 140000h to 14FFFFh 130000h to 13FFFFh 120000h to 12FFFFh 110000h to 11FFFFh 100000h to 10FFFFh 0F0000h to 0FFFFFh 0E0000h to 0EFFFFh 0D0000h to 0DFFFFh 0C0000h to 0CFFFFh 0B0000h to 0BFFFFh 0A0000h to 0AFFFFh 090000h to 09FFFFh 080000h to 08FFFFh 070000h to 07FFFFh 060000h to 06FFFFh 050000h to 05FFFFh 040000h to 04FFFFh 030000h to 03FFFFh 020000h to 02FFFFh 010000h to 01FFFFh 00E000h to 00FFFFh 00C000h to 00DFFFh 00A000h to 00BFFFh
(x16) Address Range 0F0000h to 0F7FFFh 0E8000h to 0EFFFFh 0E0000h to 0E7FFFh 0D8000h to 0DFFFFh 0D0000h to 0D7FFFh 0C8000h to 0CFFFFh 0C0000h to 0C7FFFh 0B8000h to 0BFFFFh 0B0000h to 0B7FFFh 0A8000h to 0AFFFFh 0A0000h to 0A7FFFh 098000h to 09FFFFh 090000h to 097FFFh 088000h to 08FFFFh 080000h to 087FFFh 078000h to 07FFFFh 070000h to 077FFFh 068000h to 06FFFFh 060000h to 067FFFh 058000h to 05FFFFh 050000h to 057FFFh 048000h to 04FFFFh 040000h to 047FFFh 038000h to 03FFFFh 030000h to 037FFFh 028000h to 02FFFFh 020000h to 027FFFh 018000h to 01FFFFh 010000h to 017FFFh 008000h to 00FFFFh 007000h to 007FFFh 006000h to 006FFFh 005000h to 005FFFh (Continued)
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MBM29LV320TE/BE80/90/10
(Continued) Sector Size Sector A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 (Kbytes/ Kwords) Sector Address SA4 SA3 SA2 SA1 SA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 X X X X X 8/4 8/4 8/4 8/4 8/4 (x8) Address Range 008000h to 009FFFh 006000h to 007FFFh 004000h to 005FFFh 002000h to 003FFFh 000000h to 001FFFh (x16) Address Range 004000h to 004FFFh 003000h to 003FFFh 002000h to 002FFFh 001000h to 001FFFh 000000h to 000FFFh
Note : The address range is A20 : A-1 if in byte mode (BYTE = VIL). The address range is A20 : A0 if in word mode (BYTE = VIH).
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MBM29LV320TE/BE80/90/10
Sector Group Address Table (MBM29LV320TE) (Top Boot Block) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 A20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 A16 X X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 X X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 X X X SA60 to SA62 A14 X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X Sectors SA0 to SA3 SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA31 SA32 to SA35 SA36 to SA39 SA40 to SA43 SA44 to SA47 SA48 to SA51 SA52 to SA55 SA56 to SA59
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MBM29LV320TE/BE80/90/10
Sector Group Address Table (MBM29LV320BE) (Bottom Boot Block) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A17 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 X X X SA8 to SA10 A14 0 0 0 0 1 1 1 1 A13 0 0 1 1 0 0 1 1 A12 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
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MBM29LV320TE/BE80/90/10
Common Flash Memory Interface Code Table Description Query-unique ASCII string "QRY" A6 to A0 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh
N
DQ15 to DQ0 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h 0016h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h (Continued)
Primary OEM Command Set 02h : AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set (00h = not applicable) Address for Alternate OEM Extended Table VCC Min Voltage (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV VCC Max (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV VPP Min voltage VPP Max voltage Typical timeout per single byte/word write 2 s Typical timeout for Min size buffer write 2N s Typical timeout per individual sector erase 2N ms Typical timeout for full chip erase 2 ms Max timeout for byte/word write 2N times typical Max timeout for buffer write 2N times typical Max timeout per individual sector erase 2 times typical Max timeout for full chip erase 2N times typical Device Size = 2N byte Flash Device Interface description 02h : x8/x16 Max number of byte in multi-byte write = 2N Number of Erase Block Regions within device Erase Block Region 1 Information
N N
1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h
Erase Block Region 2 Information
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(Continued) Description Query-unique ASCII string "PRI" A6 to A0 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh DQ15 to DQ0 0050h 0052h 0049h 0031h 0031h 0000h 0002h 0004h 0001h 0004h 0000h 0000h 0000h 00B5h 00C5h 00XXh
Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 00h = Required Erase Suspend 02h = To Read & Write Sector Protection X = Number of sectors in per group Sector Temporary Unprotection 01h = Supported Sector Protection Algorithm Number of Sector for Bank 2 00h = Not Supported Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported VACC (Acceleration) Supply Minimum DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV VACC (Acceleration) Supply Maximum DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV Boot Type 02h = MBM29LV320BE 03h = MBM29LV320TE
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MBM29LV320TE/BE80/90/10
FUNCTIONAL DESCRIPTION
1. Read Mode The device has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. Assuming the addresses have been stable for at least tACC-tOE time. When reading out data without changing addresses after power-up, input hardware reset or to change CE pin from "H" or "L". 2. Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition the current consumed is less than 5 A Max During Embedded Algorithm operation, VCC active current (ICC2) is required even when CE = "H". The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L"). Under this condition the current consumed is less than 5 A Max Once the RESET pin is taken high, the device requires tRH as wake up time for outputs to be valid for read access. In the standby mode the outputs are in the high impedance state independently of the OE input. 3. Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of the device data. This mode can be useful in the application such as a handy terminal which requires low power consumption. To activate this mode, the device automatically switches themselves to low power mode when the device addresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 A (CMOS Level). During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically, and the device read the data for changed addresses. 4. Output Disable With the OE input at logic high level (VIH), output from the device is disabled. This will causes the output pins to be in a high impedance state. 5. Autoselect Autoselect mode allows reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are DON'T CARES except A6, A1, and A0 (A-1). (See "MBM29LV320TE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" in DEVICE BUS OPERATIONS.) The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "MBM29LV320TE/BE Command Definitions Table" (DEVICE BUS OPERATIONS) (See "2. Autoselect Command" in COMAND DIFINITIONS). 26
Retired Product DS05-20894-5E_July 31, 2007
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Word 0 (A0 = VIL) represents the manufacturer's code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device identifier code. Word 3 (A1 = A0 = VIH) represents the extended device code. These three bytes/words are given in "MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" (DEVICE BUS OPERATIONS). In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See "MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in DEVICE BUS OPERATIONS.) 6. Write The device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the device function. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever starts first. Standard microprocessor write timings are used. See "Read Only Operation Characteristics" in AC CHARACTERISTICS for specific timing parameters. 7. Sector Group Protection The device features hardware sector group protection. This feature disables both program and erase operations in any combination of twenty five sector groups of memory. See "Sector Group Address Tables (MBM29LV320TE/ BE)" in FLEXIBLE SECTOR-ERASE ARCHITECTURE. The sector group protection feature is enabled using programming equipment at the user's site. The device is shipped with all sector groups unprotected. To activate it, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL and A6 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. "Sector Address Tables (MBM29LV320TE/BE)" in FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of the seventy one (71) individual sectors, and "Sector Group Address Tables (MBM29LV320TE/BE)" in FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See "14. Sector Group Protection Timing Diagram" in TIMING DIAGRAM and "5. Sector Group Protection Algorithm" in FLOW CHART for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) produces a logic "1" code at device output DQ0 for a protected sector. Otherwise the device produces "0" for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON'T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply VIL on byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical "1" at DQ0 for a protected sector group. See "MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in DEVICE BUS OPERATIONS for Autoselect codes. 8. Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the device in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. See "15. Temporary Sector Group Unprotection Timing Diagram" in TIMING DIAGRAM and "6. Temporary Sector Group Unprotection Algorithm" in FLOW CHART. 9. Extended Sector Group Protection
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In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The extended sector group protection requires VID on RESET pin only. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins), and write extended sector group protection command (60h). A sector group is typically protected in 250 s. To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a logic "1" at device output DQ0 will produce for protected sector in the read operation. If the output is logic "0", please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (See "16. Extended Sector Group Protection Timing Diagram" in TIMING DIAGRAM and "7. Extended Sector Group Protection Algorithm" in FLOW CHART.) 10. RESET Hardware Reset The device resets by driving RESET pin to VIL. The RESET pin has pulse requirement and has to be kept low (VIL) for at least "tRP" in order to properly reset internal state machine. Any operation in the process of being executed is terminated and the internal state machine is reset to the read mode "tREADY" after the RESET pin is driven low. Furthermore once the RESET pin goes high, the device requires an additional "tRH" before it allows read access. When the RESET pin is low, the device is in the standby mode for the duration of the pulse and all the data output pins are tri-stated. If a hardware reset occurs during program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See "10. RESET, RY/BY Timing Diagram" in TIMING DIAGRAM for the timing diagram. See "8. Temporary Sector Group Unprotection" for additional functionality. 11. Boot Block Sector Protection The Write Protection function provides hardware method of protecting certain boot sectors without using VID. This function is provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two "outermost" 8 K byte boot sectors (MBM29LV320TE : SA69 and SA70, MBM29LV320BE : SA0 and SA1) independently of whether those sectors are protected or unprotected using the method described in "Sector Group Protection". The two outermost 8 K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8 K byte boot sectors were last set to be protected or unprotected. That is, sector group protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in "Sector Group Protection". 12. Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group becomes temporarily unprotected. The system uses fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore the present sequence is used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See "17. Accelerated Program Timing Diagram" in TIMING DIAGRAM. Erase operation during Accelerated Program Operation is strictly prohibited. 28
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COMMAND DEFINITIONS
The device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "MBM29LV320TE/BE Command Definitions Table" in DEVICE BUS OPERATIONS defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. 1. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remain enabled for reads until the command register contents are altered. The device automatically powers up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles retrieves array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. See "AC CHARACTERISTICS" for the specific timing parameters. 2. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the command write, a read cycle from address (XX) 00h retrieves the manufacture code of 04h. A read cycle from address (XX) 01h for x16 ((XX) 02h for x8) returns the device code. A read cycle from address (XX) 03h for x16 ((XX) 06h for x8) returns the extended device code. (See "MBM29LV320TE/BE Sector Group Protection Verify Autoselect Codes Table" and "Extended Autoselect Code Table" in DEVICE BUS OPERATIONS.) The sector state (protection or unprotection) is informed by address (XX) 02h for x16 ((XX) 04h for x8). Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logic "1" at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See "MBM29LV320TE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" in DEVICE BUS OPERATIONS.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, writing Read/Reset command sequence must precede the Autoselect command. 3. Byte/Word Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device automatically provides adequate internally generated program pulses and verify programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location being programmed.
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The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which the device return to the read mode and addresses are no longer latched. See "Hardware Sequence Flags Table". Therefore the device requires that a valid address to the device be supplied by the system at this particular instance of time. Hence Data Polling must be performed at the memory location being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. "1. Embedded ProgramTM Algorithm" in FLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. 4. Chip Erase Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The system can determine the erase operation status by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is "1" (See "12. Write Operation Status".) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming) "2. Embedded EraseTM Algorithm" in FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 5. Sector Erase Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever starts later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of "tTOW" from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors are erased concurrently by writing the six bus cycle operations on "MBM29LV320TE/BE Command Definitions Table" in DEVICE BUS OPERATIONS. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be reenabled after the last Sector Erase command is written. A time-out of "tTOW" from the rising edge of last CE or WE whichever starts first initiates the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever starts first occurs within the "tTOW" time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see "16. DQ3", Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (See "12. Write Operation Status" for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70). Sector erase does not require the user to program the device prior to erase. The device automatically program all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function). When erasing 30
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a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling), DQ6 (Toggle Bit), or RY/BY. The sector erase begins after the "tTOW" time out from the rising edge of CE or WE whichever starts first for the last sector erase command pulse and terminates when the data on DQ7 is "1" (See "12. Write Operation Status".) at which the device return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase "2. Embedded EraseTM Algorithm" in FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 6. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The addresses are "DON'T CARES" when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin is at high impedance state and the DQ7 bit is at logic "1", and DQ6 stops toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation is suspended. Further writes of the Erase Suspend command are ignored. When the erase operation is suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. See "17. DQ2". After entering the erase-suspend-read mode, the users can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode causes DQ2 to toggle. The end of the erase-suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point is ignored. Another Erase Suspend command is written after the chip resumeds erasing. 7. Extended Command (1) Fast Mode Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. The read operation is also executed after exiting this mode. During the Fast mode, do not write any command other than the Fast program/Fast mode reset command. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (See "8. Embedded ProgramTM Algorithm for Fast Mode" in FLOW CHART.) The VCC active current is required even CE = VIH during Fast Mode.
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(2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (See "8. Embedded ProgramTM Algorithm for Fast Mode" in FLOW CHART.) (3) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of device. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. See "Common Flash Memory Interface Code Table" in FLEXIBLE SECTOR-ERASE ARCHITECTURE for details. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrieves device information. Please note that output data of upper byte (DQ15 to DQ8) is "0" in word mode (16 bit) read. See "Common Flash Memory Interface Code Table" in FLEXIBLE SECTOR-ERASE ARCHITECTURE. To terminate operation, it is necessary to write the read/reset command sequence into the register. (See "Common Flash Memory Interface Code Table" in FLEXIBLE SECTORERASE ARCHITECTURE.) 8. HiddenROM Region The HiddenROM feature provides a Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field. The HiddenROM region is 256 bytes in length and is stored at the same address of the "outermost" 8 K byte boot sector. The MBM29LV320TE occupies the address of the byte mode 3FFFC0h to 3FFFFFh (word mode 1FFFE0h to 1FFFFFh) and the MBM29LV320BE type occupies the address of the byte mode 000000h to 000080h (word mode 000000h to 000040h) . After the system writes Enter HiddenROM command sequence, the system can read the HiddenROM region by using the addresses normally occupied by the boot sector. That is, the device sends all commands that would normally be sent to the boot sector to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sector. 9. HiddenROM Entry Command The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it is protected. However once it is protected, it is impossible to unprotect so please use this with caution. HiddenROM area is 256 byte and in the same address area of "outermost" 8 K byte boot block. Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called as HiddenROM mode when the HiddenROM area appears. Sector other than the boot block area could be read during HiddenROM mode. Read/Program of the HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. 10. HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the program command in usual except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address other than the HiddenROM area is selected to program, data of the address will be changed.
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Please note that the sector erase command is prohibited during HiddenROM mode. If the sector erase command is appeared in this mode, data of the address will be erased. 11. HiddenROM Protect Command There are two methods to protect the HiddenROM area. One of them is to write the sector group protect setup command (60h) , set the sector address in the HiddenROM area and (A6, A1, A0) = (0,1,0) , and write the sector group protect command (60h) during the HiddenROM mode. The same command sequence could be used because it is the same with the extension sector group protect except that it is in the HiddenROM mode and it does not apply high voltage to RESET pin. Please see "9. Extended Sector Group Protection" in FUNCTIONAL DESCRIPTION for details of extention sector group protect setting. The other is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A6, A1, A0) = (0,1,0) , and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A1, A0) = (0,1,0) and the sector address in the HiddenROM area, and read. When "1" appears on DQ0, the protect setting is completed. "0" will appear on DQ0 if it is not protected. Please apply write pulse agian. The same command sequence could be used for the above method because other than the HiddenROM mode, it is the same as the sector group protect in the past. Please see "7. Sector Group Protection" in FUNCTIONAL DESCRIPTION for details of the sector group protect setting. Other sector group will be effected if the address other than those for HiddenROM area is selected for the sector group address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest attention. 12. Write Operation Status Details in "Hardware Sequence Flags Table" are all the status flags that can be used to check the status of the device for current mode operation. During sector erase, the part provides the status flags automatically to the I/O ports. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are in erase. Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. If the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. Hardware Sequence Flags Table Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Suspended Mode Erase Suspend Read (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Time Limits Embedded Erase Algorithm Erase Suspended Mode Erase Suspend Program (Non-Erase Suspended Sector) DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 0 1 0 Data 0 0 1 0 DQ2 1 Toggle *1 Toggle Data 1 *2 1 N/A N/A
In Progress
*1: Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle. *2: Reading from non-erase suspend sector address indicates logic "1" at the DQ2 bit.
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13. DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device produces a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read device produces true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read device produces a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read device produces a "1" on DQ7. The flowchart for Data Polling (DQ7) is shown in "3. Data Polling Algorithm" ( FLOW CHART). For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased, not a protected sectors. Otherwise, the status may be invalid. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte's valid data the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend mode or sector erase time-out. (See "Hardware Sequence Flags" Table.) See "6. Data Polling during Embedded Algorithm Operation Timing Diagram" in TIMING DIAGRAM for the Data Polling timing specifications and diagrams. 14. DQ6 Toggle Bit I The device also features the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data from the device results in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 stops toggling and valid data is read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In program operation, if the sector being written to be protected, the toggle bit toggles for about 1 s and then stops toggling with data unchanged. In erase operation, the device erases all selected sectors except for ones that are protected. If all selected sectors are protected, chip toggles the toggle bit for about 400 s and then drop back into read mode, having data unchanged. Either CE or OE toggling causes DQ6 to toggle. See "7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram" in TIMING DIAGRAM for the Toggle Bit I timing specifications and diagrams. 15. DQ5 Exceeded Timing Limits DQ5 indicates if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 produces a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of device under this condition. The CE circuit partially powers down device under these conditions (to approximately 2 mA) . The OE and WE pins 34
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control the output disable functions as described in "MBM29LV320TE/BE User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" (DEVICE BUS OPERATIONS). The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never read valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5 bit indicates a "1." Please note that this is not a device failure condition since device was incorrectly used. If this occurs, reset device with command sequence. 16. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 remains low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or Toggle Bit I indicates device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low ("0") , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Hardware Sequence Flags Table". 17. DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector causes DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or erase, or erase suspend program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 are used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also "Toggle Bit Status Table" and "8. DQ2 vs DQ6" in TIMING DIAGRAM. Furthermore, DQ2 is used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. 18. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first read. If the toggle bit is not toggling, indicates that the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see "15. DQ5") . If it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.
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The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. See "4. Toggle Bit Algorithm" in FLOW CHART.
Toggle Bit Status Table Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle DQ2 1 Toggle*1 Toggle 1*2
*1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle. *2 : Reading from non-erase suspend sector address indicates logic "1" at the DQ2 bit. 19. RY/BY Ready/Busy The device provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If output is low, the device is busy with either a program or erase operation. If output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands. If the device is placed in an Erase Suspend mode, RY/BY output is high. During programming, RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin indicates a busy condition during RESET pulse. See "9. RY/BY Timing Diagram during Program/Erase operations" and "10. RESET, RY/BY Timing Diagram" in TIMING DIAGRAM for a detailed timing diagram. RY/BY pin is pulled high in standby mode. Since this is an open-drain output, the pull-up resistor needs to be connected to VCC ; multiples of devices may be connected to the host system via more than one RY/BY pin in parallel. 20. Byte/Word Configuration BYTE pin selects byte (8-bit) mode or word (16-bit) mode for device. When this pin is driven high, the device operates in word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin becomes the lowest address bit, and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ15 to DQ8 and the DQ7 to DQ0 bits are ignored. See "11. Word Mode Configuration Timing Diagram", "12. Byte Mode Configuration Timing Diagram" and "13. BYTE Timing Diagram for Write Operations" in TIMING DIAGRAM the detail . 21. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up device automatically resets internal state machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. 36
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22. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, write cycle is locked out for VCC less than VLKO (Min) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device resets to the read mode. Subsequent writes are ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (Min) . If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used. 23. Write Pulse "Glitch" Protection Noise pulses of less than 3 ns (Typ) on OE, CE, or WE does not initiate write cycle. 24. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be logical zero while OE is a logical one. 25. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH does not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up.
26. Sector Group Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids both write and erase commands that are addressed to protected sectors. Any commands to write or erase addressed to protected sector are ignore. (See "7. Sector Group Protection" in FUNCTIONAL DESCRIPTION.)
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MBM29LV320TE/BE80/90/10
ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, and RESET *1, *2 Power Supply Voltage *1 A9, OE, and RESET *1, *3 WP/ACC * *
1, 4
Symbol Tstg TA VIN, VOUT VCC VIN VACC
Rating Min -55 -40 -0.5 -0.5 -0.5 -0.5 Max +125 +85 VCC + 0.5 +4.0 +13.0 +13.0
Unit C C V V V V
*1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or l/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. * 3: Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC) does not exceed +9.0 V.Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. * 4: Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +13.0 V which may overshoot to +12.0 V for periods of up to 20 ns when VCC is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature Power Supply Voltage* Symbol TA VCC Part No. MBM29LV320TE/BE 80/90/10 MBM29LV320TE/BE 80/90 MBM29LV320TE/BE 10 Value Min -40 +3.0 +2.7 Max +85 +3.6 +3.6 Unit C V
* : Voltage is defined on the basis of VSS = GND = 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
+0.6 V -0.5 V -2.0 V
20 ns
20 ns
20 ns
Maximum Undershoot Waveform
20 ns
VCC + 2.0 V VCC + 0.5 V +2.0 V
20 ns 20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V +13.0 V VCC + 0.5 V
20 ns Note : This waveform is applied for A9, OE, and RESET. 20 ns
Maximum Overshoot Waveform 2
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MBM29LV320TE/BE80/90/10
DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current Symbol ILI ILO ILIT Conditions VIN = VSS to VCC, VCC = VCC Max VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9, OE, RESET = 12.5 V CE = VIL, OE = VIH, f = 5 MHz VCC Active Current *1 ICC1 CE = VIL, OE = VIH, f = 1 MHz VCC Active Current *2 VCC Current (Standby) VCC Current (Standby, Reset) VCC Current (Automatic Sleep Mode) *3 WP/ACC Accelerated Program Current Input Low Voltage Input High Voltage Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration Voltage for Autoselect and Sector Group Protection (A9, OE, RESET) *4 Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage ICC2 ICC3 ICC4 CE = VIL, OE = VIH VCC = VCC Max, CE = VCC 0.3 V, RESET = VCC 0.3 V VCC = VCC Max, WE/ACC = VCC 0.3 V, RESET = VSS 0.3 V VCC = VCC Max, CE = VSS 0.3 V, RESET = VCC 0.3 V VIN = VCC 0.3 V or VSS 0.3 V VCC = VCC Max, WP/ACC = VACC Max IOL = 4.0 mA, VCC = VCC Min IOH = -2.0 mA, VCC = VCC Min IOH = -100 A Byte Word Byte Word Min -1.0 -1.0 - 0.5 2.0 11.5 Max +1.0 +1.0 35 16 18 7 7 40 5 5 Unit A A A mA mA mA A A A mA V V V
ICC5
5
IACC VIL VIH VACC
20 + 0.6 VCC + 0.3 12.5
VID VOL VOH1 VOH2 VLKO
11.5 2.4 VCC - 0.4 2.3
12.5 0.45 2.5
V V V V V
* 1: The ICC current listed includes both the DC operating current and the frequency dependent component. * 2: ICC active while Embedded Algorithm (program or erase) is in progress. * 3: Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns. * 4: Applicable for only VCC applying.
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AC CHARACTERISTICS
* Read Only Operations Characteristics Symbol Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE to BYTE Switching Low or High JEDEC Standard tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH Condition CE = VIL OE = VIL OE = VIL 80 0 80* Min Max 80 80 30 25 25 20 5 90 0 90 90 35 30 30 20 5 Value 90* Min Max 10* Min Max 100 0 100 100 35 30 30 20 5 ns ns ns ns ns ns ns s ns Unit
* : Test Conditions : Output Load : 1 TTL gate and 30 pF (MBM29LV320TE80, MBM29LV320BE80) 100 pF (MBM29LV320TE90/10, MBM29LV320BE90/10) Input rise and fall times : 5 ns Input pulse levels : 0.0 V or 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V
3.3 V Diode = 1N3064 or Equivalent Device Under Test 6.2 k CL Diode = 1N3064 or Equivalent
2.7 k
Notes : CL = 30 pF including jig capacitance (MBM29LV320TE80, MBM29LV320BE80) CL = 100 pF including jig capacitance (MBM29LV320TE90/10, MBM29LV320BE90/10) Test Conditions
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* Write/Erase/Program Operations Symbol Parameter
JEDEC Standard
Min
Value 80 (Note)
Typ Max Min
90 (Note)
Typ Max Min
10 (Note)
Typ Max
Unit
Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle and Data Polling
tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL Byte Word tWHWH1 tWHWH2
2 3
tWC tAS tAH tDS tDH tOEH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tOESP tCSP tRB tRP tRH
80 0 45 30 0 0 10 0 0 0 0 0 0 35 35 25 25 50
8 16 1

90 0 45 35 0 0 10 0 0 0 0 0 0 35 35 30 30 50
8 16 1
100 0 45 35 0 0 10 0 0 0 0 0 0 35 35 30 30 50 8 16 1

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s ns ns s s s s ns ns ns
Read Recover Time Before Write Read Recover Time Before Write (OE High to CE Low) CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Programming Operation Sector Erase Operation *1 VCC Setup Time Rise Time to VID * Rise Time to VACC *

2
500 500 4 4 4 0 100
500 500 4 4 4 0 100
500 500 4 4 4 0 100
Voltage Transition Time *2 Write Pulse Width *2 OE Setup Time to WE Active * CE Setup Time to WE Active * Recover Time From RY/BY RESET Pulse Width RESET High Level Period Before Read
2

500 200
500 200
500 200
(Continued)
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(Continued) Symbol Parameter
JEDEC Standard
Min
Value 80 (Note)
Typ Max Min
90 (Note) 30 80 90 80 20 50 30 90 90 90 20 50
10 (Note)
Max
Unit
Typ Max Min Typ
BYTE Switching Low to Output High-Z BYTE Switching High to Output Active Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time

tFLQZ tFHQV tBUSY tEOE tTOW tSPD
50

30 90
ns ns ns ns s s
100
100 20
*1 : This does not include the preprogramming time. *2 : This timing is for Sector Group Protection operation. *3 : This timing is limited for Accelerated Program operation only.
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MBM29LV320TE/BE80/90/10
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle Limits Min 100,000 Typ 1 16 8 Max 10 360 300 100 Unit s s s s cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead
TSOP (1) PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance CIN COUT CIN2 CIN3 Symbol VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Condition Value Typ 6.0 8.5 8.0 15.0 Max 7.5 12.0 10.0 20.0 Unit pF pF pF pF
Notes : * Test conditions TA = + 25 C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance.
FBGA PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance CIN COUT CIN2 CIN3 Symbol VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Condition Value Typ 6.0 8.5 8.0 15.0 Max 7.5 12.0 10.0 20.0 Unit pF pF pF pF
Notes : * Test conditions TA = + 25 C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipulated by output capacitance.
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TIMING DIAGRAM
* Key to Switching Waveforms
WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L" Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Change from H to L Will Change from L to H Changing State Unknown Center Line is HighImpedance "Off" State
1. Read Operation Timing Diagram
tRC
Address
tACC
Address Stable
CE
tOE tDF
OE
tOEH
WE
tCE High-Z tOH High-Z
Outputs
Output Valid
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MBM29LV320TE/BE80/90/10
2. Hardware Reset/Read Operation Timing Diagram
tRC
Address
tACC
Address Stable
CE
tRH
tRP
tRH
tCE
RESET
tOH High-Z
Outputs
Output Valid
3. Alternate WE Controlled Program Operation Timing Diagram
3rd Bus Cycle Data Polling PA tAS tAH PA tRC
Address
555h tWC
CE
tCS tCH tCE
OE
tGHWL tWP tWPH tOE tWHWH1
WE
tDS tDH tDF tOH
Data
A0h
PD
DQ7
DOUT
DOUT
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates last two bus cycles out of four bus cycle sequence. * These waveforms are for the x16 mode. The addresses differ from x8 mode.
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4. Alternate CE Controlled Program Operation Timing Diagram
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CE
tDS tDH PD DQ7 DOUT
Data
A0h
Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates last two bus cycles out of four bus cycle sequence. * These waveforms are for the x16 mode. The addresses differ from x8 mode.
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MBM29LV320TE/BE80/90/10
5. Chip/Sector Erase Operation Timing Diagram
Address
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA*
CE
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS AAh tDH 55h 80h AAh 55h
10h for Chip Erase 10h/ 30h
Data
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for Chip Erase. Note : These waveforms are for the x16 mode. The addresses differ from x8 mode.
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6. Data Polling during Embedded Algorithm Operation Timing Diagram
CE
tCH
tOE
tDF
OE
tOEH
WE
tCE *
DQ7
Data
DQ7
DQ7 = Valid Data
High-Z
tWHWH1 or 2
DQ6 to DQ0
Data tBUSY
DQ6 to DQ0 = Output Flag tEOE
DQ6 to DQ0 Valid Data
High-Z
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation) .
7. Toggle Bit I during Embedded Algorithm Operation Timing Diagram
CE
tOEH
WE
OE
tDH
* DQ6 = Toggle DQ6 = Toggle DQ6 = Stop Toggling tOE
DQ0 to DQ7 Data Valid
DQ6
Data (DQ0 to DQ7)
* : DQ6 = Stops toggling. (The device has completed the Embedded operation.)
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8. DQ2 vs. DQ6
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
WE
Erase Suspend Read
DQ6
DQ2 *
Toggle DQ2 and DQ6 with OE or CE
* : DQ2 is read from the erase-suspended sector.
9. RY/BY Timing Diagram during Program/Erase Operations
CE
Rising edge of the last write pulse
WE
Entire programming or erase operations
RY/BY
tBUSY
10. RESET, RY/BY Timing Diagram
WE
RESET
tRP tRB
RY/BY
tREADY
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11. Word Mode Configuration Timing Diagram
CE
tCE
BYTE DQ14 to DQ0
tELFH Data Output
(DQ7 to DQ0)
Data Output (DQ14 to DQ0)
tFHQV A-1 DQ15
DQ15/A-1
12. Byte Mode Configuration Timing Diagram
CE
BYTE DQ14 to DQ0
tELFL
Data Output (DQ14 to DQ0) tACC
Data Output
(DQ7 to DQ0)
DQ15/A-1
DQ15 tFLQZ
A-1
13. BYTE Timing Diagram for Write Operations
Falling edge of last write signal
CE or WE
BYTE
tAS
Input Valid tAH
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14. Sector Group Protection Timing Diagram
A20, A19, A18 A17, A16, A15 A14, A13, A12
SPAX
SPAY
A6, A0
A1
VID VIH A9 VID VIH OE
tVLHT tWPP tVLHT tVLHT tVLHT
WE
tOESP
CE
tCSP
Data
tVCS tOE
01h
VCC
SPAX : Sector Group Address to be protected. SPAY : Next Sector Group Address to be protected. Note : A-1 is VIL on byte mode.
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15. Temporary Sector Group Unprotection Timing Diagram
VCC
tVCS
tVIDR tVLHT
VID VIH RESET
CE
WE
tVLHT Program or Erase Command Sequence tVLHT
RY/BY
Unprotection period
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MBM29LV320TE/BE80/90/10
16. Extended Sector Group Protection Timing Diagram
VCC
tVCS
RESET
tVIDR
tVLHT tWC tWC SPAX SPAX SPAY
Address
A6, A0
A1
CE
OE
tWP
TIME-OUT
WE Data
60h 60h 40h tOE 01h 60h
SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min)
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17. Accelerated Program Timing Diagram
VCC
tVCS
tVACCR tVLHT
VACC VIH WP/ACC
CE
WE
tVLHT Program Command Sequence tVLHT
RY/BY
Acceleration period
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MBM29LV320TE/BE80/90/10
FLOW CHART
1. Embedded ProgramTM Algorithm
EMBEDDED ALGORITHM
Start
Write Program Command Sequence (See Below)
Data Polling Embedded Program Algorithm in progress
No
Verify Data ? Yes
Increment Address
No
Last Address ? Yes
Programming Completed
Program Command Sequence (Address/Command): 555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Notes: * The sequence is applied for x 16 mode. * The addresses differ from x 8 mode.
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2. Embedded EraseTM Algorithm
EMBEDDED ALGORITHM
Start
Write Erase Command Sequence (See Below)
Data Polling Embedded Erase Algorithm in progress
No
Data = FFh ? Yes Erasure Completed
Chip Erase Command Sequence (Address/Command): 555h/AAh
Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h Sector Address /30h Sector Address /30h Sector Address /30h
555h/10h
Additional sector erase commands are optional.
Note : The sequence is applied for x 16 mode. The addresses differ from x 8 mode.
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3. Data Polling Algorithm
Start
Read Byte (DQ7 to DQ0) Addr. = VA Yes
DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA
VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation
DQ7 = Data? * No Fail
Yes
Pass
* : DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
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4. Toggle Bit Algorithm
Start
Read DQ7 to DQ0 Addr. = "H" or "L" *1 Read DQ7 to DQ0 Addr. = "H" or "L"
DQ6 = Toggle? Yes No
No
DQ5 = 1? Yes *1, *2 Read DQ7 to DQ0 Addr. = "H" or "L" *1, *2
Read DQ7 to DQ0 Addr. = "H" or "L"
DQ6 = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command
No
Program/Erase Operation Complete
*1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to "1".
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5. Sector Group Protection Algorithm
Start
Setup Sector Group Addr. A20, A19, A18, A17,A16, A15, A14, A13, A12
(
)
PLSCNT = 1
OE = VID, A9 = VID, CE = VIL, RESET = VIH A6 = A0 = VIL, A1 = VIH
Activate WE Pulse Increment PLSCNT Time out 100 s
WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group
SPA, ( Addr. = = A0 =A1 = VIH )* A6 VIL No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector Group ? No Device Failed Remove VID from A9 Write Reset Command Yes
Sector Group Protection Completed
* : A-1 is V IL on byte mode.
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6. Temporary Sector Group Unprotection Algorithm
Start
RESET = VID *1
Perform Erase or Program Operations
RESET = VIH
Temporary Sector Group Unprotection Completed *2
*1 : All protected sectors groups are unprotected. *2 : All previously protected sectors groups are protected once again.
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7. Extended Sector Group Protection Algorithm
Start
RESET = VID Wait to 4 s Device is Operating in Temporary Sector Group Unprotection Mode No
Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Protect Sector Group Write 60h to Sector Address (A6 = A0 = VIL, A1 = VIH)
Time out 250 s
Increment PLSCNT
To Verify Sector Group Protection Write 40h to Sector Address (A6 = A0 = VIL, A1 = VIH) Read from Sector Group Address (A0 = VIL, A1 = VIH, A6 = VIL)
No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command No Data = 01h? Yes Protection Other Sector Group ? No Remove VID from RESET Write Reset Command Device Failed Sector Group Protection Completed
Setup Next Sector Group Address
Yes
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8. Embedded ProgramTM Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
Set Fast Mode
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling In Fast Program Verify Data? Yes Increment Address No Last Address ? Yes Programming Completed No
XXXXh/90h Reset Fast Mode XXXXh/F0h
Notes : * The sequence is applied for x 16 mode. * The addresses differ from x 8 mode.
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MBM29LV320TE/BE80/90/10
ORDERING INFORMATION
MBM29LV320 T E 80 TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Normal Bend TR = 48-Pin Thin Small Outline Package (TSOP) Reverse Bend PBT = 63-Ball Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29LV320 32Mega-bit (4 M x 8-Bit or 2 M x 16-Bit) Flash Memory 3.0 V-only Read, Program, and Erase
Part No. MBM29LV320TE80TN MBM29LV320TE90TN MBM29LV320TE10TN MBM29LV320TE80TR MBM29LV320TE90TR MBM29LV320TE10TR MBM29LV320TE80PBT MBM29LV320TE90PBT MBM29LV320TE10PBT MBM29LV320BE80TN MBM29LV320BE90TN MBM29LV320BE10TN MBM29LV320BE80TR MBM29LV320BE90TR MBM29LV320BE10TR MBM29LV320BE80PBT MBM29LV320BE90PBT MBM29LV320BE10PBT
Package 48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend 48-pin plastic TSOP (1) (FPT-48P-M20) Reverse Bend 63-pin plastic FBGA (BGA-63P-M01) 48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend 48-pin plastic TSOP (1) (FPT-48P-M20) Reverse Bend 63-pin plastic FBGA (BGA-63P-M01)
Access Time(ns) 80 90 100 80 90 100 80 90 100 80 90 100 80 90 100 80 90 100
Remarks
Top Sector
Bottom Sector
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PACKAGE DIMENSIONS
48-pin plastic TSOP(1) (FPT-48P-M19)
Note 1) *: Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15(.006)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
LEAD No.
1 48
INDEX
Details of "A" part
0.25(.010)
0~8
0.600.15 (.024.006)
24
25
20.000.20 (.787.008) * 18.400.20 (.724.008)
* 12.000.20
(.472.008) 1.10 -0.05
+0.10 +.004
.043 -.002 (Mounting height)
0.50(.020)
"A"
0.10(.004)
0.17 -0.08 .007 -.003
C
+0.03 +.001
0.100.05 (.004.002) (Stand off height) 0.220.05 (.009.002) 0.10(.004)
M
2003 FUJITSU LIMITED F48029S-c-6-7
Dimensions in mm (inches) . Note : The values in parentheses are reference values. Note 1) *: Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15(.006)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
48-pin plastic TSOP(1) (FPT-48P-M20)
LEAD No.
1 48
INDEX
Details of "A" part 0.600.15 (.024.006)
0~8 0.25(.010)
24
25
0.17 -0.08
+0.03 +.001
0.10(.004)
.007 -.003 0.50(.020)
0.220.05 (.009.002)
0.10(.004)
M
0.100.05 (.004.002) (Stand off height)
"A"
1.10 -0.05
+0.10 +.004
* 18.400.20
(.724.008) 20.000.20 (.787.008)
.043 -.002 (Mounting height)
* 12.000.20(.472.008)
C
2003 FUJITSU LIMITED F48030S-c-6-7
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
(Continued)
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MBM29LV320TE/BE80/90/10
(Continued) 63-pin plastic FBGA (BGA-63P-M01)
11.000.10(.433.004) 1.05 -0.10
+0.15 +.006
(8.80(.346)) (7.20(.283)) (5.60(.220)) 0.80(.031)TYP
.041 -.004 (Mounting height) 0.380.10 (.015.004) (Stand off)
8 7 6 7.000.10 (.276.004) (4.00(.157)) (5.60(.220)) 5 4 3 2 1 M INDEX AREA INDEX BALL 63-o0.450.05 (63-o0.18.002) 0.08(.003)
M
L
K
J
H
G
F
E
D
C
B
A
0.10(.004)
C
2001 FUJITSU LIMITED B63001S-c-2-2
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
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MBM29LV320TE/BE80/90/10
Revision History
Revision DS05-20894-5E July 31, 2007
The following comment is added. This product has been retired and is not recommended for new designs. Availability of this document is retained for reference and historical purposes only.
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MBM29LV320TE/BE80/90/10
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94088-3470, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ F0305 (c) FUJITSU LIMITED Printed in Japan
Retired Product DS05-20894-5E_July 31, 2007
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

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